eASIC nextreme




UMMC DDR_X Controller

UMMC DDR_X Controller



  • Supports multiple port sizes
  • For ports with AXI Interface
    • Compatibility with AMBA AXI protocol (AXI Version 1.0)
    • Support for AXI burst types: incremental and wrap
  • For ports with AHB interface
    • Compatibility with AMBA AHB specification, rev, 2.0
    • Support for all AHB burst types: single, incr, wrap
  • System interface clock asynchronous/synchronous to MC clock
  • System data bus width may be different from MC data bus width (Optional)
  • Supports QoS through various arbitration schemes
    • Round robin
    • Port priority and programmable bandwidth per port
    • Weighted round robin
  • Supports APB interface for Software/Configuration Register
  • Configurable and programmable address mapping
  • Configurable request queue depth
  • Configurable data buffer depth
  • Supports memory standards
    • DDR3
    • DDR4
    • LPDDR2
    • LPDDR3
  • Supports up to 4 ranks
  • Supports industry standard DFI 3.1 interface
    • Supports following MC clock to PHY clock ratio
      • 1:1 (Full-rate Mode)
      • 1:2 (Half-rate Mode)
      • 1:4 (Quarter rate Mode)
  • Supports different memory interface data width 8, 16, 32, 64 (72 with ECC enabled)
    • Supports 128-bit/256-bits memory interface data width (controllers operate in gang mode to access a 128-bit/256-bit memory device)
  • Supports different memory burst length 4, 8, 16
  • Supports partial population of memories where not all memory byte lanes are populated with memory chips
  • Supports active/precharge power down
  • Supports hardware/software driven self refresh entry and exit
  • Supports auto-refresh and per-bank refresh
  • Supports ECC checking and correction (optional)
    • With read modify write (partial write)
    • Without read modify write
  • Supports automated memory initialization
  • Supports ZQ calibration
  • Supports different request processing techniques
    • In-order request processing
    • Out of order request processing for better performance
  • Supports programmable memory timing parameters
  • Supports ODT
  • Supports intelligent request scheduling
    • Read/Write grouping
    • Refresh scheduling based on user traffic