eASIC nextreme




WISHBONE Bus

WISHBONE Bus



  • Simple, compact, logical IP core hardware interfaces that require very few logic gates
  • Supports structured design methodologies used by large project teams
  • Full set of popular data transfer bus protocols including:
    • READ/WRITE cycle
    • BLOCK transfer cycle
    • RMW cycle
  • Modular data bus widths and operand sizes
  • Supports both BIG ENDIAN and LITTLE ENDIAN data ordering
  • Variable core interconnection methods support point-to-point, shared bus,
crossbar switch, and switched fabric interconnections
  • Handshaking protocol allows each IP core to throttle its data transfer speed
  • Supports single clock data transfers