eASIC and golden gate technology announce the adoption of critical EDA software to support structured ASIC design
June 6, 2004
eASIC chose Golden Gate’s “Power Saving” EDA flow to provide customers with a comprehensive and efficient Structured ASIC solution
Santa Clara, California, June 5, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, and Golden Gate Technology, a developer of power driven physical design tools, today announced the adoption of two products from Golden Gate’s GoPower suite. The IC-Plan and PowerPlacer tools will be used for eASIC’s Structured eASIC array. With this cooperation, the partners will incorporate Golden Gate’s clock aware physical design into eASIC’s tools set for Structured ASIC, responding to the market requirements of less power consumption, reduced wire length and guaranteed routability. As part of the agreement, two of Golden Gate’s products, the advanced power managing floorplanner (IC Plan) and the advanced power reducing placer (PowerPlacer), will be integrated into eAISC’s tools kit for designer’s use.
“We are excited to have this opportunity with eASIC”, said Dr. Michael Burstein, CEO of Golden Gate Technologies. “Golden Gate’s advanced floorplanner and placer work well with the Structured eASIC product family. Our tools will work together with existing eASIC tools at a stage in the flow that has a significant impact on design closure.”
“Golden Gate’s physical design tools are very important for addressing today’s deep submicron ASIC design challenges,” said Zvi Or-Bach, eASIC President and CEO. “After evaluating the tools, eASIC was very impressed with the Golden Gate’s PowerPlacer quick run-time, reduced wire length and superior routability. We found it is a perfect match for our customer’s needs. Using Golden Gate’s floorplanner helps us in providing design-friendly Structured ASIC, which is NRE-free, removing design-entry barrier and allowing low-cost and high performance ASIC. This integration of powerful EDA tools and innovative technology allows us to create a comprehensive Structured eASIC offering from RTL to complete physical design.”
Production release of the Structured eASIC tools set is slated for Q4 CY 04.
eASIC® has developed a breakthrough Structured ASIC technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. eASIC’s technology enables rapid and low-cost ASIC and System-on-Chip designs by its innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.
Headquartered in San-Jose California, eASIC Corporation is a privately held company, founded in 1999 by Zvi Or-Bach, the founder of Chip Express. Or-Bach is viewed by many as the “father of Structured ASIC technology”.
About Golden Gate Technology
Golden Gate Technology Inc. was founded in 2001 with the goal of building power driven physical design tools targeting very deep submicron system-on-chip circuits. GGT has a proven management team with years of experience in the EDA industry. The company has an R&D team of more than 40 engineers. GGT’s major product offering, GoPower, has received customer acceptance and is currently in production design flows. The company aims to be a major supplier of physical design tools in the EDA industry.
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