eASIC Announced Immediate Availability of Aeroflex Gaisler’s LEON4 Processor
March 3, 2010
New LEON4 core delivers 50% Performance Increase
Santa Clara, CA – March 03, 2010 – eASIC Corporation, a supplier of NEW ASICs, today announced the immediate availability of Aeroflex Gaisler’s next generation LEON processor, the LEON4, as part of its eZ-IP Alliance Core Library. LEON4 is a high performance, 32-bit processor core based on the SPARC V8 architecture. The new LEON4 core complements the widely used LEON3 processor for high-performance embedded applications across a broad spectrum of demanding consumer and industrial applications.
The power and size optimized LEON4 is fully software compatible with previous LEON processors, yet with a performance increase of up to 50% at the same clock frequency. The LEON4 processor implements single-cycle load/store instructions, as well as static branch prediction. The register file and internal load/store data paths have been extended to 64-bits, while the data cache and bus interface can be either 64- or 128-bit wide. An optional Level-2 (L2) cache has also been added to the architecture, further improving performance on data intensive and multi-core applications. The LEON4 processor delivers up to 1.7 DMIPS per MHz or 0.35 SPECINT2000/MHz.
“We are pleased with the performance of this next generation processor on eASIC silicon,” said Jiri Gaisler, CTO and Founder of Aeroflex Gaisler. “The low cost-point and low up-front development cost of eASIC devices coupled with our LEON4 embedded processing sub-systems now enable an excellent price/performance entry point for custom embedded chip designs.”
“The LEON4 processor core provides our customers with a perfect alternative to traditional soft processor cores from FPGA vendors and prevents customers from being locked into proprietary FPGA vendor IP cores,” said Jasbinder Bhoot, Vice President, Worldwide Marketing at eASIC Corporation. “With Gaisler, customers are provided complete solutions that include CPU cores, peripherals, software tool chain, development boards and technical support.”
The LEON4 is a high-performance 32-bit SPARC V8 processor that provides computing capabilities to cost-sensitive embedded microcontroller applications. The processor is available as a soft core together with a rich IP library (GRLIB) for instantiations into both FPGAs for prototyping, and eASIC devices for volume production.
Learn more at eASIC eZ-IP Alliance
eASIC is a fabless semiconductor company offering breakthrough NEW ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer a new generation of ASICs with significantly lower up-front costs than traditional ASICs.
Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information on eASIC please visit www.eASIC.com