eASIC Announces Nextreme-3 Platform Support for PCIe Gen 3.1 – SRIS
August 11, 2015
Nextreme-3 enables scalable, high bandwidth, cabled connectivity with SATA-Express using PCIe Gen 3.1
SANTA CLARA, Calif. – August 11, 2015 – eASIC® Corporation (@easic), a fabless semiconductor company that delivers a custom integrated circuit (IC) platform (eASIC Platform) today announced immediate availability of silicon-proven transceivers optimized for the PCIe 3.1 electrical specification.
The eASIC Nextreme-3 family incorporates transceivers that feature advanced receiver clock-data recovery (CDR) circuits, enabling them to operate with separate reference clocks between link ends with independent spread-spectrum modulation, in keeping with the SRIS (separate refClks independent spread) usage model. Coupled with advanced equalization capabilities and low power consumption, the transceivers are ideal for use in a wide variety of high performance storage and networking systems.
eASIC support for SRIS allows data communication over a cable without requiring a separate cable for forwarding the reference clock, which significantly reduces electromagnetic interference (EMI) issues while allowing use of lighter, lower cost cables. It also provides scalable, high bandwidth connectivity and compatibility with future SATA/SAS [serial advanced technology attachment/serial attached SCSI (small computer system interface)] standards.
“Our eASIC Nextreme-3 platform now offers designers the freedom to create server-independent, scale-out storage solutions,” said Brent Przybus, senior director of marketing at eASIC. “The small footprint of our devices, together with versatile configuration options, gives OEMs a compact, low cost and low power solution.”
eASIC is a semiconductor company offering a differentiated solution that enables us to rapidly and cost-effectively deliver custom ICs, creating value for our customers’ hardware and software systems. Our eASIC solution consists of our eASIC platform which incorporates a versatile, pre-defined and reusable base array and customizable single-mask layer, our ASICs, delivered using either our easicopy or standard ASIC methodologies, and our proprietary design tools.
We believe this innovative technology allows eASIC to offer the optimal combination of fast time-to-market, high performance, low power consumption, low development cost and low unit cost for our customers. eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Crescendo Ventures, Seagate Technology, Kleiner Perkins Caufield and Byers (KPCB) and Evergreen Partners.