eASIC announces successful implementation of its configurable
August 20, 2001
The 0.15 micron eASICore® test chip indicates high density and performance and features unique via-configurable I/Os
San Jose, California, August 20, 2001 — eASIC Corporation today announced that it has completed the implementation of its eASICore, a configurable logic core, using UMC’s 0.15µm,
7 metal-layer process. The eASICore test chip comprises 24 embedded cores (eCores), featuring about 600K configurable logic gates, and via-configurable I/O pads called eI/Os. The results of the eASICore testing indicate high performance and high-density, in accordance with the engineering characterization.
As the eASICore is proven in UMC silicon, it reduces the design risk and allows customers of both companies to enjoy the advantages of an accelerated development cycle and low-cost derivatives for various platform-based and System-on-Chip (SoC) designs. Such a platform could use a single silicon base set for a wide range of high volume applications.
“The configurable logic core is an emerging technology that is essential for today’s SoC designs which require increased speed and flexibility and reduced cost,” said Zvi Or-Bach, President and CEO of eASIC. “Since semiconductor tooling cost approaches $1 million per design, it is critical to use configurable logic cores allowing multiple designs to share the same mask-set in order to save cost, react quickly to market fluctuation, and extend the design life cycle. Existing ASIC technologies have become prohibitively expensive. Only 1,000 designs out of the traditional 10,000 ASIC designs per year can justify the tooling and NRE costs of 0.13µm process. eASICore is the missing building block for SoC and platform-based designs providing optimized cost, performance and time- to-market.”
eASICore is a hard, configurable IP core, of about 25K usable logic gates. This configurable logic core is ideal for networking and communication applications. Users can map arbitrary logic onto the eASICore using standard ASIC synthesis tools, and perform placement and routing using standard ASIC P&R tools. The customization of the eASICore is performed by bit-stream loading of SRAM-based logic and using a single custom mask for the interconnect. The 0.15µm eASICore, implemented in UMC’s 7 metal-layer process, uses the lower 3 metal layers for the logic fabric, leaving 4 metal layers for interconnects. Two connectivity options are available:
- For a small array of eASICores, two metal layers could be used for the eASICore while reserving the top two for over-the-cell routing.
- For a large array of eASICores, all four metal layers could be used for eASICore’s interconnections, utilizing a patent pending single-via mask customization.
The eASICore includes a built-in low-skew, low-power, clock tree and built-in scan chain.
eASICore’s proprietary technology allows configurable logic blocks to be embedded into user designs in a fast, easy to implement and cost-effective manner. This breakthrough technology combines SRAM Look-Up-Table cells with mask-customizable interconnection.
eASICore’s technology takes advantage of the Look-Up-Table approach to logic implementation proven in FPGA technology, while avoiding the deficiencies of SRAM-programmable interconnect. This is made possible by eASIC’s mask-configured, metal-to-metal interconnection. The result is significantly reduced silicon area and production cost. The performance of eASICore is much better than FPGA’s, since the eASICore interconnect delay is significantly lower (10 to 100 times) than the SRAM-programmable interconnect used in FPGA technology. The eASICore delivers close to Standard Cell performance and density together with FPGA ease-of-design and time-to-market.
eIO – Via-Configurable I/O Pads
The eI/O – via-configurable I/O pad – is an innovative technique developed to allow an additional level of flexibility for platform-based designs utilizing eASICore’s technology. With the unique via configurable I/O capability (eI/O), all available I/Os of comparable Standard Cell libraries are provided based on a single generic I/O structure, configured through a single custom via layer.
Each pad can be configured as INPUT, OUTPUT, BI-DIRECTIONAL or SUPPLY.
Using only via-configuration, the pad characteristics can be changed as follows.
The INPUT section can be programmed for:
Type: regular CMOS/LVTTL or Schmitt
Inversion: non-inverting or inverting
The OUTPUT section can be programmed for:
Keeper: pullup, pulldown, or keeper
Drive: 2 to 24 mA in 9 steps
Slew: normal or slow
The SUPPLY section can be programmed for:
GND: Ground to core and input I/O section
VDD: Power (1.5V) to input I/O section
VDDE: Power (1.5V) to chip core
VCC: Power (3.3V) to output I/O section
VSS: Ground to output I/O section
The 0.15µm eASICore was tested and implemented in UMC’s silicon. The IP product is now available for customers.
eASIC Corporation is pioneering a breakthrough approach of configurable logic cores for System-on-Chip and platform-based designs. Its configurable logic IP core, called eASICore, offers high performance and density with ease-of-design, rapid time-to-market and reduced development cost.
eASIC Corporation is a privately held company based in San Jose, California. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania.
eASIC’s technology is protected by US patents: US 6,194,912, US 6,236,229, US 6,245,634 and additional pending patents. Legal Notices
Contact: Jasbinder (Jazz) Bhoot
Senior Director, Marketing
Tel: (408) 855-3028
Fax: (408) 855-9201