eASIC completes implementation of its configurable logic core in TSMC 0.18 micron process
April 23, 2001
eASICore® test results in silicon indicate high performance and high density
San Jose, California, April 23, 2001 — eASIC® Corporation, the technology innovator of configurable logic IP cores, today announced that the company has successfully implemented its eASICore® in TSMC’s silicon at 0.18 micron, 6 metal-layer process. Clear indication of high performance and density of the eASICore® was obtainable following the completion of the engineering characterization. eASIC® provided the design data to TSMC for test chip fabrication used for qualifying the manufacturing process and eventually lowering the risk for the customer. This will enable Fabless companies as well as Integrated Device Manufacturers who use TSMC foundry services, to enjoy the eASICore® advantages of high performance, low development cost and design flexibility.
“We developed the eASICore® to address the market need for an efficient ASIC solution for deep sub-micron system-on-chip designs,” stated Zvi Or-Bach eASIC President and CEO.” With the currently available ASIC technologies, the cost of mask-sets required for semiconductor fabrication is increasing exponentially as we move to lower process geometry. Qualifying the eASIC® technology in silicon at the foundry leader TSMC will enable immediate implementation of the eASICores as an embedded configurable logic or memory IP core within SoCs, while using conventional fabrication process but reducing the number of mask-sets, which translates into major time and cost savings.”
Peyman Kazemkhani, IP Alliance program director of TSMC said, “By adding eASICore® to our IP Alliance portfolio, we are providing our customers with an important building block of configurable logic for high-performance SOC designs. This in turn supports our commitment to lowering the barriers of entry to high-performance SOC design for designers worldwide.”
The eASICore® architecture is based on proprietary technology that provides an efficient solution for embedding configurable logic blocks in a fast, easy to implement and cost-effective method. This technology is rooted in a breakthrough concept of combining an SRAM Look-Up-Table cell with metal mask programmable interconnection. This combination allows delivering close to Standard Cell performance and density together with FPGA time-to-market and ease-of-design. Additionally, the eASIC® technology addresses the issues of huge silicon area and circuit delay resulted from the programmable routing in existing FPGA devices.
The eASICore® technology takes advantage of the already proven Look-Up-Table approach for logic implementation, while avoiding the deficiencies of SRAM programmable routing. This is made possible since the routing of the eASICore® is performed through metal-to-metal interconnection, which utilizes a much smaller silicon area and reduces the SoC production cost. Furthermore, the resulting delay of the eASICore® routing is significantly (10 to 100 times) lower compared to SRAM controlled pass transistor devices and therefore the eASICore® performance is similar to Standard Cell.
The eASICore® and the supporting EDA tools are available today for implementation in silicon by chip developers who use TSMC’s 0.18µm process technology.
TSMC IP Alliance
TSMC’s IP Alliance encompasses the industry’s largest catalog of silicon-verified and production-proven foundry specific intellectual property. Vendor cores are validated in TSMC silicon under the CyberShuttle multiproject wafer program to ensure the best possible design experience, easiest design reuse, and the fastest integration into an overall system design. The IP Alliance’s best-of-class IP offerings feature high-performance, system-level cores including embedded processors, digital signal processors, and communications and networking IP, special memories, bus interfaces, RF and mixed-signal modules, multimedia IP and programmable logic. All cores in the TSMC catalog are directly sold and supported by the individual IP vendor to better support each customer’s particular design and business model. Each TSMC process-proven IP core complies with TSMC design rules and models.
The licensing fee and the royalties are determined per customer, depending on the expected volume and the number of eASICores used.
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology, library and IP options and other leading-edge foundry services. TSMC operates two six-inch wafer fabs and six eight-inch wafer fabs. The Company also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and WaferTech. In 2000, TSMC produced the foundry industry’s first 300mm customer wafers and began constructing two dedicated 300mm fabs. TSMC’s corporate headquarters are in Hsin-Chu, Taiwan. More information about TSMC is available through the World Wide Web at www.tsmc.com.
eASIC® Corporation is pioneering a breakthrough approach of embedded configurable ASIC cores for System-on-Chip designs. This configurable ASIC core, called eASICore®, offers high performance and density with ease-of-design, rapid time-to-market and low design development cost.
eASIC® Corporation is a privately held company based in San Jose, California. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania. www.eASIC.com
As TSMC’s IP Alliance partner, eASIC will be participating in the TSMC Technology Symposium, being held in four US locations: San Jose, CA (4-23), Austin, TX (4-25), Boston, MA (4-27), and Costa Mesa, CA (4-30).
Contact: eASIC Corporation
Jasbinder (Jazz) Bhoot
Senior Director, Marketing
Tel: (408) 855-3028
Fax: (408) 855-9201
TSMC North America