eASIC Introduces eTools 8.0
November 16, 2009
New eTools 8.0 Software Simplifies 45nm ASIC Design
Santa Clara, CA – November 16, 2009 – eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of its eTools 8.0 software suite for implementing 45nm eASIC Nextreme-2 designs. The eTools 8.0 tool suite delivers a robust ASIC grade design flow with the simplicity, ease of design, and a cost point that is normally associated with FPGA design tools. By focusing on ease-of-use, and low cost of entry, eASIC is now enabling designers to make a seamless transition to adopting eASIC Nextreme-2 devices as a lower cost and lower power alternative to FPGAs and a lower NRE alternative to traditional ASICs.
The eTools 8.0 software suite includes a number of new capabilities that simplify the transition path for designers looking to adopt the advantages of eASIC Nextreme-2 devices. These include a user friendly GUI-based design environment (Design Navigator), IP-wizards that facilitate easier integration of IP blocks; a new power estimation tool that enables power estimation based on the RTL; and an easy to use floor planning tool for making optimal macro placements. Designers have the option of performing synthesis using Magma Talus RTL or Synopsys DC tools.
Unlike traditional standard cell ASIC flows, the eTools 8.0 flow enables designers to focus their efforts on achieving their desired functionality and timing and not on arduous complex deep submicron ASIC tasks such as power mesh design, signal integrity, test insertion, DFM (design for manufacture) and clock insertion. As a result, designers are able to rapidly progress from their initial RTL to a netlist-level handoff to eASIC. eASIC Nextreme-2’s unique and patented single-via based configuration technology enables eASIC engineers to rapidly tape-out and deliver prototypes in 6 to 8 weeks.
“eASIC is committed to the goal of making ASIC design achievable and affordable for the masses. We are seeing more and more FPGA designers use our technology to reduce the cost and power of their designs. With eTools 8.0 we are taking a giant step on the ease-of-use axis, thus enabling designers to create a rapid, low cost, low risk path to ASIC,” said Dr. Ranko Scepanovic, Senior Vice President, Software and Advanced Technology at eASIC Corporation.
FPGA and ASIC designers can try a free 30-day evaluation of eTools 8.0 and Magma Talus RTL software by visiting Request eTools page.
eASIC is a fabless semiconductor company offering breakthrough NEW ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer a new generation of ASICs with significantly lower up-front costs than traditional ASICs.
Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information on eASIC please visit www.eASIC.com
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