eASIC Technology Helps ST Microelectronics Achieve a Landmark: 24 Hours From RTL to Tapeout Using eASIC’s Innovative Configurable Logic Technology
April 4, 2005
(The printer platform chip tape-out employed Direct-write eBeam customization, eliminating NRE cost)
San Jose, California, April 25, 2005 — eASIC® Corporation, a provider of Configurable Logic and Structured ASIC products, today announced that its customer STMicroelectronics achieved 24 hours turnaround from RTL to tape-out using eASIC’s Structured eASIC technology. ST has licensed eASIC’s 0.13µ eASICore® for the rapid customization of a printer platform, which allows ST to offer fast and easy customization of a printer system controller, as well as image processing personalization, in a standard pre-verified printer-engine architecture. ST’s engineering team was able to ship the final GDS-II files to the silicon fab for eBeam customization in less than a day from the time RTL was received. The eBeam customization, which is maskless, takes only a few hours for Structured eASIC devices since just a single Via layer needs to be written.
“In an ongoing effort to meet our customer’s escalating needs, STMicroelectronics has developed programmable platforms and ASSPs that provide the required flexibility for new applications and configurability for printer products,” said Vittorio Peduto, General Manager of Computer Systems Division at STMicroelectronics. “Our goal is to obtain state-of-the-art design capabilities that make it easier for us to deliver leading-edge IC’s, therefore we engaged with eASIC for its breakthrough configurable logic technology. We benefited 24hr design turn around time from RTL to tape out. With eASIC’s technology we can make very efficient use of our Direct-write eBeam equipment and eliminate the high cost of mask for customization.”
“STMicroelectronics and eASIC achieved this industry milestone by working together to efficiently employ eASIC’s configurable logic fabric within the Printer Platform chip,” said Zvi Or-Bach, CEO and founder of eASIC Corporation. “We are delighted with our joint work with a technology leader like STMicroelectronics who has already recognized the tremendous potential and importance of Direct-write e-Beam. This achievement demonstrates how a user of the eASIC configurable logic technology has been able to reach the goal of customizing high density logic chips in a matter of days. This new reality of rapid design with no NRE is becoming available for high end applications in the form of domain specific platforms by STMicroelectronics and for the main stream in the form of FlexASIC structured ASIC solution we are rolling out jointly with Flextronics Semiconductors.”
Maskless Customization Approach for NRE-Free Structured ASIC
eASIC’s innovative customization technique enables eliminating multimillion-dollar mask sets cost using Direct-write e-Beam customization approach for ICs. Based on the company’s breakthrough via-customization technology, eASIC’s fabric yields about ten times higher throughput of Direct-write e-Beam machines, compared to metal customization. This is made possible as Vias occupy about 1% of the customization layer area, while metal occupies at least 30% of the area, which impacts the direct-writing time and operation cost. Moreover, as only a single Via-layer is required for Structured eASIC customization, it further shortens the turnaround time and eventually cuts the cost.
eASIC is the only company offering ASIC without NRE cost. Although FPGAs do not require NRE either, their per-unit cost is dramatically higher than ASIC’s and their performance is lower by about an order of magnitude. e-Beam Direct-write customization is a preferred alternative for Structured eASIC prototyping and low volume while for higher volumes, a single Via-mask is generated for the routing customization. No additional engineering efforts are required when moving to higher volumes, as the same GDSII files are used for the single Via customization with either eBeam or conventional lithography mask. In order to complement the efficient interconnect routing with design flexibility advantages, the logic cells in the Structured eASIC fabric are customized with bit-stream and Look-Up-Tables (LUTs), similar to FPGAs. This unique combinations that employs different customization techniques for routing and logic cells, creates an optimal Structured ASIC solution that provides ease-of-design together with low cost and high performance. In addition, the bit-stream logic customization allows for an easy post-fabrication debug and hence shorter time-to-market.
eASIC® has developed a breakthrough Configurable Logic technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. Its Structured eASIC architecture enables rapid and low-cost ASIC and SoC (System-on-Chip) designs by innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.
eASIC Corporation is a privately held company, Venture Capital backed by Kleiner Perkins Caufield and Byers. Headquartered in San-Jose, California, eASIC was founded in 1999 by Zvi Or-Bach, the founder of Chip Express who is viewed by many as the “father of Structured ASIC technology”.
Jasbinder (Jazz) Bhoot
Senior Director, Marketing
Tel: (408) 855-3028
Fax: (408) 855-9201