Monterey teams with eASIC to provide core-centric hierarchical design solution
January 12, 2002
eASICores Combine with Monterey’s System-Driven Physical Design Tools to Raise the Level of Physical Abstraction
SUNNYVALE, California – January 12, 2002 — Monterey Design Systems and eASIC Corporation today announced a strategic agreement to provide the industry’s first core-centric hierarchical design solution. The combination of eASIC’s eASICore® configurable cores and Monterey’s System-Driven Physical Design solution raises the level of physical design abstraction from gates to functional cores, providing dramatic improvements in designer productivity and turnaround time. Engineers at Monterey and eASIC have been working together over the past year to develop a core-based design environment that yields significant productivity gains for large ASIC and SoC designs.
“Monterey’s hierarchical methodology fits in very well with our approach of providing configurable cores for use as the basic building blocks of complex IC designs,” said Ze’ev Wurman, Vice President of Software at eASIC. “We believe that the deployment of eASICores in conjunction with Monterey design tools will enable our customers to realize the goals of high-performance, rapid turnaround time, and low cost for their mission critical IC designs.”
“eASICore is an ideal complement to Monterey’s hierarchical methodology that uses complex cores as building blocks for multi-million gate SoC designs,” said Dave Reed, Vice President of Marketing and Solutions Delivery for Monterey. “eASIC provides the building blocks and Monterey the tools to form an unbeatable combination that enables our customers to thrive in today’s competitive marketplace.”
One of the most challenging aspects of intellectual property (IP) reuse is integration of existing IP cores into a functional chip design. By developing and packaging an integration environment based on Monterey’s SDPD tools together with eASICores, eASIC provides a much more complete package than they would otherwise be able to offer. The inclusion of SDPD tools dramatically reduces the time and effort required to integrate the configurable cores into complex chip designs.
eASIC Corporation is pioneering a breakthrough ASIC design methodology while maintaining standard manufacturing process. The company is offering a Universal Fabric for IC design along with configurable logic cores for System-on-Chip and platform-based designs. eASIC’s products allow achieving high performance and density together with ease-of-design, rapid time-to-market and reduced product development cost. eASIC Corporation is a privately held company based in San Jose, California, tel: 408-264-7128. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania.
Note to Editors: eASIC and eASICore are registered trademarks of eASIC Corporation. (See Legal Notice). All other trademarks and registered trademarks are the property of their respective owners.
About Monterey Design Systems
Monterey Design Systems is privately held and partners with leading EDA companies such as Cadence and Synopsys to ensure interoperability in ASIC and COT design flows.
Monterey Design Systems is located at 894 Ross Drive, Sunnyvale, CA 94089-1443, Tel: 1.408.747.7370, fax: 1.408.747.7377
Note to Editors: Monterey, Monterey Design Systems, and Dolphin are registered trademarks and System-Driven Physical Design and Sonar are trademarks of Monterey Design Systems. All other trademarks and registered trademarks are the property of their respective owners.
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