eASIC nextreme

Principal Signal Integrity Power Engineer

Position: Principal Signal Integrity Power Engineer
Location: Santa Clara, CA, USA
Job ID: E892017

Job Summary / Objective

This position, reporting directly into the Sr. Director, Applications Engineering, will be responsible for the design and simulation for a variety of core IP’s. They will interface with IP vendors, customers and various teams inside eASIC to ensure a successful and competitive product. All work is expected to be of highest production quality and is expected to enable implementation teams to deliver in a timely fashion to hit market windows. The position requires a self-driven candidate with very good knowledge on design and verification as well as good communication skills.

Essential Functions

The successful candidate should have an excellent track record in the following areas:

  • Signal integrity, power integrity and channel modeling
  • Power integrity analysis for each PWR/GND domain: package extraction, simulation and decoupling strategy
  • PDN methodology development: simultaneous switching noise/output (SSN or SSO) analysis for each I/O PWR/GND domain
  • High speed I/O package design for PCI-E I & II, XAUI, 10G SerDes, FSB, DDR I, II, III and IV
  • Flip-chip bump or wirebond pad re-arrangement for chip-package-board co-design
  • Optimal layer stackup and PWR/GND plane/island assignment to minimize voltage drop/noise/coupling
  • Crosstalk analysis and reduction
  • Design and model characterization boards, load boards, and system level test boards
  • EMI reduction and shielding techniques
  • Writing specification for design teams
  • Presenting design trade-off analyses and implementation recommendations with custom circuit designers


  • Detail oriented
  • Strong written and verbal communication skills
  • Strong collaboration skills
  • Strong technical skills (knowledge of Verilog, SystemVerilog or VHDL)

Manager / Supervisory Responsibilities

This position has no direct supervisory responsibilities, but does serve as a coach and mentor for other positions in the department and lead projects.

Work Environment

This job operates in a professional technical environment. This role routinely uses standard office equipment such as computers, phones and photocopiers.


Minimal travel is expected for this position.

Required Education and Experience

  • BSEE required; MSEE preferred
  • Minimum of 12 years of professional experience in a semiconductor industry, in a research and development environment
  • Experience with signal and power integrity analysis
  • Experience with lab equipment for high-speed digital systems
  • Experience with correlating simulation/silicon results
  • Excellent technical communication through presentations and documentation
  • Familiarity with the following tools and flows: Hspice, Sigrity (Power SI/XcitePI), Apache (Redhawk/Sentinel-PI), ANSYS (Q3D, HFSS, SIwave)
  • 5 or more years of hands on experience in design, characterization, debug of high Speed SERDES ranging from 1Gbps to 32Gbps
  • Self-starter with the ability to manage multiple projects with simultaneous time sensitive deadlines
  • Ability to function independently while maintaining strong team-work and collaborative approach
  • Highly motivated with strong interpersonal skills
  • Strong written and verbal communication skills

EEO Statement

eASIC provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, national origin, age, disability or genetics. In addition to federal law requirements, eASIC complies with applicable state and local laws governing nondiscrimination in employment in every location in which the company has facilities.

Other Duties

Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities and activities may change at any time with or without notice.

Click here to submit your resume.