eASIC nextreme

Senior IP Implementation Engineer

Position: Sr. IP Implementation Engineer
Location: Santa Clara, CA, USA
Job ID: 101817

Job Summary/Objective

This position, reporting into the Sr. Director IP Engineering, will be responsible for the implementation of IP macros, and support of the Customer Engineering team. This includes RTL and SDC checking, simulation of eASIC IP and, in some cases, customer netlists, synthesis, placement and routing, timing analysis, integration of critical IP such as high speed SERDES and Formal Verification. The objective is to apply the best-known methods on eASIC methodologies and achieve eASIC’s objective of delivering silicon working Right First Time – On Time (RFT-OT).

Essential Functions

The role is responsible for timing closure, automation of implementation scripts and timing constraints development for IPs. Additional duties include (but not limited to):

  • Performing RTL checks
  • Running synthesis of IP RTL
  • Performing placement and routing, timing driven
    • This will require advanced scripting capabilities, to allow reuse
  • Running parasitic extraction and Static Timing Analysis
  • Performing Formal Verification
  • Develop simulation environment for RTL and netlists
  • Productize and qualify IPs for release to customers and Customer Engineering team
  • Reviewing and/or writing documentation
    • Datasheets of IP macros
    • Integration guides of IP
  • Customer interaction regarding IP integration


  • Detail oriented
  • Strong written and verbal communication skills
  • Strong collaboration skills
  • Strong technical skills (knowledge of Verilog, SystemVerilog or VHDL, SDC)
  • Ability to drive complex EDA tools with scripts (Perl, TCL)

Manager/Supervisory Responsibilities

This position has no direct supervisory responsibilities.

Work Environment

This job operates in a professional technical environment. This role routinely uses standard office equipment such as computers and phones.


Some travel is expected for this position ~15%. Travel can be international.

Required Education and Experience

  • BSEE required, MSEE preferred
  • 7+ years of related experience (semiconductor experience preferred)
  • Strong knowledge of chip design flow
  • Passion for technology, commitment to driving results and ability to get into the details
  • Self-starter with the ability to manage multiple projects with simultaneous time sensitive deadlines
  • Ability to function independently while maintaining strong team-work and collaborative approach
  • Highly motivated with strong interpersonal skills

EEO Statement

eASIC provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, national origin, age, disability or genetics. In addition to federal law requirements, eASIC complies with applicable state and local laws governing nondiscrimination in employment in every location in which the company has facilities.

Other Duties

Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities and activities may change at any time with or without notice.

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