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General Use Restrictions

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Trademarks

eASIC, eASICore, FlexASIC and “The configurable logic company” are registered trademarks of eASIC Corporation in the United States of America and/or other countries. eCore is an abbreviation of eASICore.

The NEW ASIC, eI/O, eRAM, bRAM, eTool, ePLD, eDebug, eMacroWare, eIP, eChip, eBIST, eMµ are trademarks of eASIC Corporation in the United States, protected by pending applications. Other company and product names may be trademarks or registered trademarks of the respective owners with which they are associated.

U.S. Government Restricted Rights

Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19.

U.S. Patents

Patent No. Title
US 6,194,912
issued Feb. 27, 2001
Integrated circuit device.
US 6,236,229
issued May 22, 2001
Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities.
US 6,245,634
issued June 12, 2001
Method for design and manufacture of semiconductors.
US 6,331,733
issued Dec. 18, 2001
Semiconductor device.
US 6,331,789
issued Dec. 18, 2001
Semiconductor device.
US 6,331,790
issued Dec. 18, 2001
Customizable and programmable cell array.
US 6,476,493
issued Nov. 5, 2002
Semiconductor device.
US 6,642,744
issued Nov. 4, 2003
Customizable and programmable cell array.
US 6,686,253
issued Feb. 3, 2004
Method for design and manufacture of semiconductors.
US 6,756,811
issued June 29, 2004
Customizable and programmable cell array.
US 6,819,136
issued Nov. 16, 2004
Customizable and programmable cell array.
US 6,930,511
issued Aug. 16, 2005
Array of programmable cells with customized interconnections.
US 6,953,956
issued Oct. 11, 2005
Semiconductor device having borderless logic array and flexible I/O.
US 6,985,012
issued Jan. 10, 2006
Customizable and programmable cell array.
US 6,989,687
issued Jan. 24, 2006
Customizable and programmable cell array.
US 7,068,070
issued June 27, 2006
Customizable and programmable cell array.
US 7,098,691
issued Aug. 29, 2006
Structured integrated circuit device.
US 7,105,871
issued Sept. 12, 2006
Semiconductor device.
US 7,157,937
issued Jan. 2, 2007
Structured integrated circuit device.

European Patents

Patent No. Title
EP 1 161 797 B1
Date of publication and mention of the grant of the patent: 22.12.2004
INTEGRATED CIRCUIT TECHNOLOGY
Date of filling: 10.03.2000
Date of publication of application: 12.12.2001

Designated contracting countries: Austria, Belgium, Switzerland, Cyprus, Germany, Denmark, Spain, Finland, France, Great Britain (UK), Greece, Ireland, Italy, Liechtenstein, Luxembourg, Monaco, Netherlands, Portugal, Sweden
EP 1 533 904 A1
Date of publication and mention of the grant of the patent: 25.05.2005
INTEGRATED CIRCUIT TECHNOLOGY
Designated contracting countries: Austria, Belgium, Switzerland, Cyprus, Germany, Denmark, Spain, Finland, France, Great Britain (UK), Greece, Ireland, Italy, Liechtenstein, Luxembourg, Monaco, Netherlands, Portugal, Sweden