eASIC nextreme




eZ-IP Intellectual Property Alliance

eZ-IP Intellectual Property Alliance



eASICs eZ-IP™ Alliance program aims to rapidly bring a wealth of fully verified eASIC ready IP cores to help you to get to market faster. Our partners are amongst the most experienced IP developers in the industry that have been carefully chosen to provide the highest quality IP cores in every aspect – from design to verification and technical support. All eZ-IP Alliance cores are off-the-shelf and pre-qualified/optimized to provide you the highest performance and/or lowest cost implementation within the chosen eASIC Nextreme family.

If you would like to qualify your IPs for eASIC devices and join the eZ-IP Alliance Partner Program please contact us.

eZ-IP Portfolio

To get access to eZ-IP datasheets please contact us.

DSP

LDPC Encoder/Decoder

LDPC Encoder/Decoder

 
Overview

Mobiveil’s LDPC Encoder / Decoder is a flash reliability solution delivering industry-leading flash endurance and retention through advanced LDPC error correction coupled with statistical digital signal processing (S-DSP) at the lowest power and smallest foot print. The Mobiveil LDPC core incorporates advanced technology in a highly scalable flash media side platform that can be tailored to customers specific application requirements from smart phones and tablets that require ultra-low power consumption, to SSDs for enterprise computing applications that demand the highest performance.

Features
  • LDPC IP scalability
    • Supporting a wide range of data-rates
    • 50MB/s to 4.0GB/s for a single LDPC instance
    • Scalable platform provides the basis for customer specific custom-LDPC cores
  • Each LDPC IP is optimized for
    • Codeword size, supports wide range of codewords
    • Maximum amount of supported parity
    • High degree of parallelism for high data-rate applications
    • Different Memory access options
    • Platform specific options (eASIC, FPGA, 40nm ASIC, 28nm ASIC)
  • All LDPC IP Cores share the following features
    • Simultaneous support for different amounts of parity
    • Simultaneous support for several LDPC codes
    • On-the-fly switching from one LDPC code to another
    • Low area and power
DPD

DPD

 
Overview

Digital PreDistortion (DPD) is a high performance technology for the linearization of radio frequency power amplifiers (RFPA). Typically DPD is used to enable non-linear RFPAs to transmit linearly whilst maintaining their beneficial high power efficiency. Thereby, DPD facilitates operational power savings plus reduced equipment bill of materials. This IP is provided in two parts:

  1. Real-time “DPD Core” implemented in RTL for the predistortion of the signal to be transmitted
  2. Non-real-time “Adaption Engine” which calculates and applies parameters to the DPD Core. This is implemented in software and readily ported for use on embedded or external micro-processors or DSPs.

Features
  • Up to 30 dB or more improvement in adjacent channel distortion depending upon the radio sub-system characteristics
  • Transmission bandwidth limited only by ASIC clock rate and the radio’s analogue sub-system
  • Agnostic with respect to PA transistor technology (e.g. LDMOS, GaN, GaS) and PA architecture (e.g. class A/B, Doherty)
  • Automatically adapts to either FDD or TDD air-access techniques
  • Provides automatic gain levelling
  • Multiple Tx channels may be supported by a single Adaption Engine processor
  • Scalable memory effect correction
  • Includes quadrature modulator effects compensation
  • No specific training or calibration required in deployment

AES128 Encryption/Decryption

 
Overview

This AES 128-bit data-path core is a simple, fully synchronous design core that supports both encryption and decryption. It can be used in many applications including: electronic financial transactions secure communications; secure video surveillance systems and encrypted data storage.

Features
  • Implemented according to the FIPS 197 documentation
  • Key size of 128, 192 and 256 bits
  • Both encryption and decryption supported
  • Fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core
  • Test benches provided

CFAR eSi-7569

 
Overview

The eSi-7569 Constant False Alarm Rate (CFAR) core is a high throughput IP core, whose main application area is target detection in radar systems. It is normally applied post-FFT in order to scan output bins for targets in noise, with a pre-designed False Alarm (FA) probability. Pre-screening the FFT output bins in hardware reduces substantially the size of data transfers to the embedded processing system, and equally reduces computationally intensive embedded processing load.

Features
  • Single clock cycle processing making it suitable for interfacing with Pipelined FFT cores
  • Parameterized input I/Q sample bit widths (max 32 bits)
  • Generalized Ordered Statistic (GOS) CFAR algorithms
  • Cell Averaging (CA) CFAR algorithms
  • Macro based configuration between asynchronous/synchronous resets
  • Macro based configuration for CFAR algorithm generation
  • AMBA 3 APB slave interface for setting real-time configurable algorithm parameters and sending target detection flags to the embedded processor

PFFT eSi-7561

 
Overview

The eSi-7561 Pipelined FFT core is a high throughput IP core that finds application in radar, wired and wireless communications.

Features
  • Fully streaming, 1 FFT point per clock cycle, no gap between packets
  • Number of FFT points can be modified at run-time
  • All power of 2 FFT sizes from and including 2 at run-time
  • Selectable forward or inverse transform at run-time
  • Per sample exponent allows exceptional dynamic range
  • Optimized 1/8 twiddle factor tables
  • Internal convergent rounding
  • Parameterized bit-widths for data and twiddle factors
  • Parameterized option to output scaling to a common exponent
  • Parameterized option to output in natural order
  • Parameterized maximum transform size from 16 to 32 K points
  • AXI4 streaming data interface

FFT/iFFT

 
Overview

The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based Digital MODEMs, to Ultrasound, RADAR and CT Image reconstruction algorithms. Although its algorithm is quite easily understood, the variants of the implementation architectures and specifics are significant and are a large time sink for hardware engineers today. The FFT v1.0 provides two different FFT architectures along with a system level fixed point C-model, and can be a drop-in replacement for FPGA Designs. To enable easy understanding of the core during simulation and design testing, RTL Verilog is provided.

Features
  • Performance up to the 300 MHz max in eASIC Nextreme-II Devices
  • Performance up to the 190 MHz max in eASIC Nextreme Devices
  • Maximum Throughput of 90 MSPS in eASIC Nextreme-II and 54 MSPS in eASIC Nextreme
  • Transform sizes from 8 to 16K points with the option to be run-time programmable
  • Two architectural implementation options providing the most area efficient implementation for a given data rate
  • A fixed point bit-accurate C-Model to enable system level analysis of eASIC FFT core
  • Drop in replacement for FPGA FFT IP to simplify cost and power reduction transition to eASIC
  • Bit width trade off (8-18 bits) enable a resource efficient implementation given the algorithmic constraints
  • Run-time configurable forward or inverse operation and scaling schedule
  • RTL Verilog Code keeps design transparent and open to the user




Encryption & Decryption

Message Digest Algorithm (MD5)

 
Overview

This core is a fully compliant implementation of the MD5 Message Digest Algorithm. It computes a 128-bit message digest for messages of up to (264 – 1) bits. Applications for this core include: electronic funds transfer, authenticated electronic data transfer and encrypted data storage.

Features
  • RFC 1321 compliant
  • Suitable for data authentication applications
  • Fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core

Secure Hash Algorithm (SHA-256) 256-bit

 
Overview

This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Applications for this core include: electronic funds transfer, authenticated electronic data transfer and encrypted data storage.

Features
  • Suitable for data authentication applications
  • Fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core

Secure Hash Algorithm (SHA-1) 160-bit

 
Overview

This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1. It computes a 160-bit message digest for messages of up to (264 – 1) bits. Applications for this core include: electronic funds transfer, authenticated electronic data transfer and encrypted data storage.

Features
  • Suitable for data authentication applications
  • Fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core

eSi-RSA

 
Overview

The eSi-RSA core is an easy to use RSA accelerator peripheral for a 32-bit APB bus.

  • ASIC or FPGA target
  • Key sizes configurable up to 4096
  • Performs all code necessary for modular exponentiation
  • Supports short public keys
  • Fully synchronous design
  • APB configuration
  • Verilog 2001

Features
  • Key sizes configurable up to 4096
  • Performs all code necessary for modular exponentiation
  • Supports short public keys
  • Fully synchronous design
  • APB configuration
  • Verilog 2001
  • Internal rams can be implemented with either bRAM or eDFF

DES Encryption/Decryption

 
Overview

This DES Crypto-processor core is a fully compliant implementation of the DES encryption and decryption algorithm. This design is a simple, fully synchronous design core. It can be used in many applications including: electronic financial transactions secure communications; secure video surveillance systems and encrypted data storage.

Features
  • NIST certified 56 bit DES implementation
  • Both encryption and decryption supported
  • Encryption and decryption performed in sixteen clock cycles
  • No dead cycles for Key loading or mode switching
  • High clock speed and low gate count achieved
  • Sustained bit rate is 4x clock speed
  • Suitable for data security applications
  • Fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core

AES32 Encryption/Decryption

 
Overview

This AES 32-bit data-path core is a simple, fully synchronous design core that supports both encryption and decryption. It can be used in many applications including: electronic financial transactions secure communications; secure video surveillance systems and encrypted data storage.

Features
  • Implemented according to the FIPS 197 documentation
  • Key size of 128, 192 and 256 bits
  • Both encryption and decryption supported
  • Fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core
  • Test benches provided




Interfaces

NVM Express Host Controller

NVM Express Host Controller

 
Overview

Mobiveil’s NVM Express Host Controller is highly flexible and configurable design targeted for both enterprise and client class solutions to unlock the current and future potential of PCIe-based SSDs. The core efficiently supports multi-core architectures ensuring thread(s) that run on each core with their own queue and interrupt without any locks required. The controller architecture is carefully tailored to optimize link and throughput utilization, latency, reliability, power consumption, and silicon footprint. Mobiveil’s NVM Express host controller can be used along with its PCI Express controller (GPEX) and any third party NAND flash controller.

Features
  • Compliant to NVM Express 1.2 specification
  • Support for configurable number of I/O queues
  • Support for configurable queue depth
  • Support for Round Robin or Weighted Round Robin with urgent priority arbitration mechanism
  • Host memory page size support of 128MB
  • Efficient and streamlined command handling
  • Supports fused operations
  • Supports all optional admin commands
  • Supports all optional NVM commands
  • Supports multi-path I/O and namespace sharing capabilities
  • Supports reservations
  • Supports multiple name spaces
  • Optional AXI interfaces for NVMe implementation in SoC
  • Well defined command interface for local CPU to perform subsystem initialization and to handle all non-hardware accelerated commands
RapidIO (GRIO) Controller

RapidIO (GRIO) Controller

 
Overview

Mobiveil Generic RapidIO (GRIO) controller is a highly flexible and configurable IP that provides a RapidIO interface on one side and a generic interface on the system side. The Mobiveil Generic RapidIO controller solution can be used as a host or device. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint. Mobiveil Generic RapidIO Controller design is fully synchronous and adheres to standard synthesis, test insertion and physical design practices. The solution allows licensees to easily migrate among COT, FPGA, eASIC, Gate array, structured ASIC and Standard cell technologies. The IP with its flexible user logic interface can be easily integrated into a wide range of applications.

Features
  • Compliant to RapidIO specifications revision 3.0
  • Compliant with RapidIO error management
  • Extension specification, revision 3.0
  • Implements logical, transport and physical layers functions
  • Architected for high link utilization and low latency
  • Efficient receive and transmit buffering scheme
  • Implements receiver controlled flow control
  • Provides packet oriented user logic interface
  • Serial and parallel interfaces supported
  • 1x, 4x,8x and 16x serial interface and 8 and 16 bits parallel interface
  • 64/128/256-bit internal data path
  • PBUS interface for configuration register access
  • Up to 256 Bytes data payload
  • Hardware error recovery
  • Exhaustive error reporting and handling
  • Pass-Through mode of operation for RIO packets up to 288 bytes
  • Accept all mode of operation for fail over support
PCI Express v3

PCI Express v3

 
Overview

The Mobiveil GPEX core is the leading high performance, silicon proven PCI Express digital controller solution from Mobiveil. The features and high degree of hardware and software configurability offered by the GPEX Controller, enable designs to be integrated in various customer applications with minimum effort. GPEX is fully compliant with PCI Express base specification version 1.0a, 1.1, 2.0 and 3.0.

Features
  • Maximum link width: X1, X2, X4, X8 or X16
  • Internal datapath width:32, 64, 128 or 256 bits
  • Flexible lane ordering and support for lane reversal
  • Supports cut-through and store-and-forward mode in RX direction
  • Efficient buffering scheme for retry buffer and receive buffer
  • Supports 8 normal functions, 16 physical functions and 64 virtual functions
  • Easy to integrate, i.e GPEX supports various ingress/egress or initiator/target based application interfaces
  • Supports SR-IOV and complaint to single root I/O virtualization and sharing specification revision 1.0
  • Supports FLR
  • Supports ATS
  • Supports ARI and compliant to address translation services revision 1.0
100-Gigabit Ethernet KR-4 MAC

100-Gigabit Ethernet KR-4 MAC

 
Overview

100-Gigabit Ethernet MAC is compliant to IEEE 802.3 KR-4 including Clause 72/73 supporting FEC, Auto-Negotiation and Link Training. The solution is fully integrated and verified with eASIC Nextreme-3 MGIO. The User-side Transmit and Receive Interface supports programmable FIFOs. The FIFOs are programmable to operate across different widths in synchronous or asynchronous mode. The Line-side Interface is by use of xMII. The Universal MAC is compatible with any PCS that implements xMII or is supplied with a PCS core.

Features
  • Full MAC/PCS IEEE 802.3 Clause 72/73 compliant
  • Includes FEC, AN and Link Training.
  • CRC-32 insertion and checking at line rate
  • Configurable IPG with DIC from 1 to 48 bytes
  • Pause frame and Jumbo frame support
  • Transmit and Receive Statistics
40-Gigabit Ethernet KR-4 MAC

40-Gigabit Ethernet KR-4 MAC

 
Overview

Tamba Networks’ 40-Gigabit Ethernet MAC is compliant to IEEE 802.3 KR-4 including Clause 72/73 supporting FEC, Auto-Negotiation and Link Training. The solution is fully integrated and verified with eASIC Nextreme-3 MGIO. The User-side Transmit and Receive Interface supports programmable FIFOs. The FIFOs are programmable to operate across different widths in synchronous or asynchronous mode. The Line-side Interface is by use of xMII. The Universal MAC is compatible with any PCS that implements xMII or is supplied with a PCS core.

Features
  • Full MAC/PCS IEEE 802.3 Clause 72/73 compliant
  • Includes FEC, AN and Link Training.
  • CRC-32 insertion and checking at line rate
  • Configurable IPG with DIC from 1 to 48 bytes
  • Pause frame and Jumbo frame support
  • Transmit and Receive Statistics
10-Gigabit Ethernet KR-4 MAC

10-Gigabit Ethernet KR-4 MAC

 
Overview

10-Gigabit Ethernet MAC is compliant to IEEE 802.3 KR-4 including Clause 72/73 supporting FEC, Auto-Negotiation and Link Training. The solution is fully integrated and verified with eASIC Nextreme-3 MGIO. The User-side Transmit and Receive Interface supports programmable FIFOs. The FIFOs are programmable to operate across different widths in synchronous or asynchronous mode. The Line-side Interface is by use of xMII. The Universal MAC is compatible with any PCS that implements xMII or is supplied with a PCS core.

Features
  • Full MAC/PCS IEEE 802.3 Clause 72/73 compliant
  • Includes FEC, AN and Link Training
  • CRC-32 insertion and checking at line rate
  • Configurable IPG with DIC from 1 to 48 bytes
  • Pause frame and Jumbo frame support
  • Transmit and Receive Statistics
CPRI IQ Cross Connect

CPRI IQ Cross Connect

 
Overview

The CPRI I/Q Cross Connect (XC) IP core that can be configured for connecting 2x2 to 36x26 bidirectional ports. The XC makes it possible to connect multiple radio units with multiple baseband resources. The switch can dynamically be configured for 1:1, broadcast and multicast operation. The XC enables routing at CPRI AxC level. The CPRI Ethernet C&M frames are routed outside the I/Q XC in a separate Ethernet switch IP which can also be delivered by Comcores. The XC is designed for baseband, C-RAN, digital DAS or advanced test systems.

Features
  • Enables AxC level cross connecting and dynamic routing
  • Highly Configurable from 2×2 to 36×36 ports
  • Support line rates 1-9 (up to 12165.12 Mbit/s)
  • Up to 64 carriers antenna carriers per port
  • 1:1, multicast, broadcast by configuration
CPRI v.6.1 Controller and PCS

CPRI v.6.1 Controller and PCS

 
Overview

Comcores’ core is a full featured implementation of the CPRI 6.1 standard. With its extreme flexibility and reduced logic consumption, the CPRI IP core is the perfect match whether the application is REC (Radio Equipment Controller) or RE (Radio Equipment). It is designed to meet or exceed the requirements of base band systems, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems. The core can be dynamically configured to handle wireless multi-mode radio systems enabling deterministic latency and high-performance throughputs required by LTE-Advanced radio base stations

Features
  • CPRI v.6.x compliance for Radio Equipment Port (RE) and Radio Equipment Controller (REC)
  • Configurable as Master / Slave
  • Daisy chaining between RE and REC with low latency interface
  • Supports Rate Options 1-9 (up to 12165.12 Mbps)
  • 8B/10B coding for backward compatibility
  • 64B/66B coding for increased data-capacity
  • Flexible mapping of IQ, VSS and C&M channels
  • Flexible IQ mapping method 1 or 3 (2 is an option)
  • Up to 64 Antenna-Carriers (AxC)
  • Fully flexible IQ sample widths and possible mix among carriers
  • Easy configurable C&M interface and vendor specific data access
  • Powerful delay management and monitoring build-in
IPC-JESD204-B

IPC-JESD204-B

 
Overview

MTI’s IPC-JESD204-B controller solution enables the quickest and most reliable integration and deployment of JESD204B interface over an eASIC Nextreme-3 device. The core enable transmit and receive implementation of the physical, data-link and transport layer of the protocol supporting MCDA-ML applications up to 12.5 Gbps and 8 lanes. The IPC-JESD204-B core is eZ-IP Level 2 qualified, fully tested and third party interoperable with a wide range of devices. The core is immediately available for design integration.

Features
  • Highest throughput
  • Highest Flexibility
  • Multi-application
  • Deterministic latency
  • Small size

Expresso DMA Bridge Core

 
Overview

The Northwest Logic Expresso DMA Bridge Core provides high-performance DMA and/or bridging between PCI Express and AXI for both Endpoint and RootPort applications. Using the core eliminates the need for the user to implement their own DMA and/or bridging design thus significantly reducing development time and risk. In addition, Northwest Logic provides companion Windows and Linux Expresso DMA Drivers. The Expresso DMA Driver works hand-in-hand with the Expresso DMA Bridge Core. Northwest Logic also provides board support packages for a wide variety of third party PCI Express boards. This support packages include a working FPGA design, Driver and GUI binaries.

Features
  • Provides high performance PCIe-AXI Bridge and/or scatter-gather DMA operation
  • Works with Northwest Logic soft Expresso Cores and FPGA hard cores
  • Provides complete RootPort Bridging support
  • Supports memory-mapped/streaming (FIFO) DMA operation
  • Can be configured with multiple DMA Channels which are independently controlled by software
  • Provides Address translations and security support
  • Supports legacy, MSI, MSI-X and local AXI interrupts

PCI Express DMA Back-End

 
Overview

The Northwest Logic DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core fully supports the eASIC Nextreme-2 family of devices.

Features
  • Provides high performance, scatter-gather DMA operation
  • Works with Northwest Logic Expresso Cores and FPGA PCI Express hard cores
  • Can be configured with multiple independent DMA Engines
  • Supports Packet/Block and Addressed/Non-addressed transfers
  • Provides simple Target and Register interfaces
  • Supports 32 and 64 bit system addressing
  • Supports legacy, MSI, MSI-X interrupts
  • Fully hardware validated and PCI-SIG certified
  • Companion Windows and Linux DMA Drivers available
  • Provided with a PCI Express Testbench
  • Delivered fully integrated with target PCI Express core
  • Minimal ASIC gate count
  • Source code available
  • Customization and Integration services available

I2S

 
Overview

The I2S-APB core integrates eight channels of Inter-IC Sound compatible serial buses. I2S is a well-known stereo audio transmission standard, widely used to connect system elements such as Analog to Digital and Digital to Analog converters.

Features
  • Meets Philips Inter-IC Sound Bus Specification
  • Supported modes
  • I2S Philips
  • Left Justified
  • Right Justified
  • DSP
  • Two clock domains
  • APB the host side clock domain
  • System clock for the I2S channels
  • Eight configurable stereo channels
  • Handshake interface to external DMA modules
  • Two sets of SCK (SCLK) and WS (LRCLK) strobes
    • one for all transmitters
    • one for all receivers
  • AMBA™ APB bus slave interface for data and configuration
  • Contains two configurable FIFO buffers
    • one for all transmit channels
    • one for all receive channels
  • One configuration register block for all channels
  • Interrupts driven by the I2S bus activity events

WISHBONE Bus

 
Overview

Features
  • Simple, compact, logical IP core hardware interfaces that require very few logic gates
  • Supports structured design methodologies used by large project teams
  • Full set of popular data transfer bus protocols including:
    • READ/WRITE cycle
    • BLOCK transfer cycle
    • RMW cycle
  • Modular data bus widths and operand sizes
  • Supports both BIG ENDIAN and LITTLE ENDIAN data ordering
  • Variable core interconnection methods support point-to-point, shared bus,
crossbar switch, and switched fabric interconnections
  • Handshaking protocol allows each IP core to throttle its data transfer speed
  • Supports single clock data transfers

UART – 16550 Compatible

 
Overview

The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a modem or other external devices, e.g. another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry standard National Semiconductors’ 16550A device.

Features
  • Wishbone interface in 8- or 32-bit data bus mode
  • FIFO only operation
  • Register level and functionality compatibility with NS16550 (but not 16450)
  • Debug interface in 32-bit data bus mode

USB 2.0

 
Overview

The CUSB2 core implements a complete high/full-speed (480/12 Mbps) peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s microprocessor on the other. It is user configurable for up to 15 IN and OUT endpoints, and includes power management and remote wake-up functions.

Features
  • Full compliance with the USB 2.0 specification
  • Control endpoint 0 – fixed 64 Bytes size
  • Configurable for up to 15 IN and 15 OUT endpoints
  • Configurable number and size of endpoints
  • Configurable single, double, triple or quad buffering
  • Programmable type of endpoints
  • Configurable 8-, 16-, or 32-bit µP interface
  • Easy integration with a wide range microprocessors and bus architectures
  • Interrupt request signals for application microprocessor
  • Interrupt vector for auto-vectored interrupts
  • UTMI Transceiver Macrocell Interface; Optional UTMI Low Pin Interface (ULPI)

USB 1.1

 
Overview

The USB 1.1 Host and Function IP core supports full speed (12Mbps) and low speed (1.5Mbps) operation, and supports the four types of USB data transfer; control, bulk, interrupt, and isochronous transfers. USB Function has four endpoints, each with their own independent FIFO. All FIFO depths are configurable via parameters.

Features
  • Includes PHY, protocol layer and endpoint
  • 8-bit WISHBONE slave bus interface
  • Includes test-bench

SPDIF Audio

 
Overview

Implements the Sony/Philips Digital Interface (SPDIF), a unidirectional and self-clocking interface for connecting digital audio equipment using linear PCM coded audio samples. The SPDIF core conforms to the IEC 60958 international standard for transmitting and receiving fast audio data.

Features
  • Conforms to the IEC 60958 International Standard
  • Programmable: supports both Receiver and Transmitter modes
  • Data mode capabilities:
    • Supports sample rates from 3kHz to 192kHz (with 98MHz SPDIF system clock)
    • 20/24 bits per sample
  • Programmable transmission rate
  • Programmable parity bit checking and generation
  • Performs master DMA handshake interfacing
  • Includes configurable internal FIFO for data streaming, with FIFO control/status signals
  • Power safe capability
  • Internal, event stimulated, interrupt request generation, with masking capability
  • Synchronization hold in the under run condition
  • Clock recovery from the SPDIF data stream
  • Detection of sample rate from the received data stream
  • Host processor interface:

    • AMBA APB slave unit to interface with the host APB controller, especially DMA
PCI Express x4 Endpoint

PCI Express x4 Endpoint

 
Overview

ASIC Architect’s PCI Express IP Cores are silicon-proven, highly configurable, scalable and ready to meet your custom design requirements. The cores come in multiple application interface data path flavors with the choice of 8-bit or 16-bit PIPE PHY Interface. The cores have been architected to achieve very low latency, high throughput, and quick timing closure with a very small silicon footprint. The user interface provides practical and integration-friendly mechanisms for the integration of the cores to the user logic.

Features
  • Multiple listings in the PCI-SIG Integrator’s list
  • Low Latency: Less than 11 clock cycles
  • Lanes Supported: x16, x8, x4, x2, x1
  • Optionally Legacy Mode Support
  • Multifunction Support up to 8
  • Multi VC Support up to 8
  • High Performance with Low Latency, Maximum Throughput
  • Multiple Pipelined Memory WR/RD Capability
  • Low Silicon Footprint
  • Highly Parameterized Core supporting both cut-through and store-and-forward schemes
  • Supports operation with 8-bit and 16-bit PIPE interface
  • Implements all optional configuration space and capability structures
  • Configurable Retry buffering scheme for low footprint and latency
  • Supports all power management states L0, L0s, L1, L2 & L3
  • Supports PCI Express Advanced Error Reporting
  • The products support the most advanced features in PCI Express – Power Management,
QoS, Hot-Plug & Hot-Swap, Data Integrity, and Error Handling

PCI Express x1, x4 Endpoint

 
Overview

This core implements a PCI Express end point controller that is compliant with PCI ExpressBase specification 1.0a, including the transaction, Data Link, and Physical protocol layers. The scalable and flexible core has a modular architecture and a high-performance,low-latency design.

Features
  • Compliant with PCI Express Base Specification 1.0a
  • Implements Transaction, Data Link, and Physical protocol layers in hardware
    Supports x1 and x4 link widths
    Offers a data rate of 2.5 Gbps per lane
    Supports up to eight Virtual Channels
    Supports lane reversal and polarity inversion
    PCI Configuration space type 0 header
    MSI capability support
    End-to-end cyclic redundancy code (ECRC) generation and checking support
    Advanced Error Reporting capability support
    Configurable TLP data payload size, from 128B to 4kB. Configurable Transmit Retry and Receive data buffers
    Modular architecture, synchronous design
    64-bit internal datapath at 125MHz
    Support for asynchronous application and core clocks
    Easy system integration through generic interface or industry standard bus interfaces module with up to 8 DMA channels (e.g., Wishbone, AMBA)
    Conforms to standard PIPE interface for compatibility with any 16-bit PIPE-compliant PHY

PCI 64/66

 
Overview

The PCI-M64 core provides a fast, fully featured, master/target interface that complies with the PCI Local Bus Specification, Rev. 2.3. It supports a 64-bit address/data bus and operates at up to 66 MHz PCI clock frequency. The 64-byte Configuration Space is extendable to 256 bytes. The Target function supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes to 2 GB.

Features
  • Zero wait states burst mode
  • Full bus Master/Target functionality
  • Single interrupt support
  • Implements 64 bytes of PCI Configuration Space registers;
    Can be extended to 256 bytes
  • Target portion supports up to six base Address Registers with both I/O
    and Memory space decoding from 16 bytes up to 2 GB
  • Support of backend initiated target retry, disconnect and abort
  • Parity generation and parity error detection.
  • Both Target and Master supported commands are: Configuration Read, Configuration
    Write, Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read
    Line (MRL) & I/O Read, I/O Write.
  • 64-bit DMA Controller Core.

PCI Express

 
Overview

The Expresso 3.0 Core is part of Northwest Logic’s PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core fully supports the eASIC Nextreme-2 family of devices.

Features
  • High-performance, easy-to-use core
  • PCI Express™ Base Specification Revision 2.1/1.1 compliant
  • x1, x2, x4, x8 lane support
  • 5.0 & 2.5 Gbit/s SERDES support
  • 1-8 Physical Function support
  • SR-IOV support with up to 255 Virtual Functions
  • Endpoint, Root Port, Upstream Switch Port, Downstream Switch Port, Bifurcation support
  • 32, 64, and 128 bit Core width support
  • Transaction Layer Bypass option AER, ECRC, MSI-X, Multi-Vector MSI, Lane Reversal support
  • Delivered fully integrated and verified with target PCIe PHY
  • Provided with a PCI Express Testbench
  • Fully validated
  • Minimal ASIC gate count
  • Customization and Integration services available

PCI Express DMA

 
Overview

The Northwest Logic Expresso DMA Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core fully supports the eASIC Nextreme-2 family of devices.

Features
  • Provided with a PCI Express Testbench
  • Delivered fully integrated with target PCI Express core
  • Minimal ASIC gate count
  • Customization and Integration services available
  • Provides high performance, scatter-gather DMA operation
  • Works with Northwest Logic Expresso Cores
  • Can be configured for up to 1024 DMA Channels
  • Supports AXI Master and Slave interfaces of selectable data widths 32,64,128 or 256-bit.
  • Supports PCIe Multi-Function and SR-IOV capability
  • Supports Endpoint and Rootport applications
  • Supports legacy, MSI, MSI-X and local AXI interrupts
  • Fully hardware validated
  • Companion Windows and Linux Expresso DMA Drivers available
  • Provided with a PCI Express Testbench

I2C Master/Slave

 
Overview

The I2C core implements a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus. The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (I2CSTA) reflects the status of I2C Bus Controller and the I2C bus.

Features
  • Master Transmitter Mode: data output through SDA while SCL outputs the serial clock
  • Master Receiver Mode: Serial data is received via SDA while SCL outputs the serial clock
  • Slave Receiver Mode – Serial data and the serial clock are received through
SDA and SCL
  • 7-bit addressing format
  • Slave Transmitter Mode – Serial data is transmitted via SDA while the serial
clock is input through SCL
  • Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
  • Bi-directional data transfer
  • Own address and General Call address detection

General Purpose I/O

 
Overview

The GP I/O IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals.

Features
  • From 1 to 32 user selectable I/Os
  • All I/Os can be bi-directional, tri-state or open-drain
  • I/Os can interrupt the CPU
  • WISHBONE compliant
  • Alternative input reference clock from external signal
  • Inputs can be registered at raising edge of system clock
  • Inputs can be registered at user programmed edge of external clock

Ethernet 10G

 
Overview

The 10 Gigabit Ethernet MAC Core is designed to comply with the IEEE802.3ae specification and meets the requirements for both WAN/MAN and LAN connectivity. Version 2 of the Core can be used in either NIC (Network Interface Card) or Ethernet Switching applications. The core can be dynamically set to terminate and form MAC frames (NIC application) or to pass MAC frames without modification to the User application or Ethernet Line (switching application).

Features
  • Full MAC layer and reconciliation sub-layer IEEE802.3ae compliant implementation
  • Passed UNH MAC, Flow-Control, Reconciliation and Interoperability tests
  • Standard preamble and SFD (Start of Frame delimiter) insertion and deletion
with optional insertion of a user specific 8-Byte preamble
  • Lane, data alignment, PHY error and local/remote fault signaling handled by
the core’s reconciliation sub-layer
  • Optional MAC address comparison on receive and overwrite on transmit
for NIC applications with programmable promiscuous mode operation

Ethernet 10/100/1000

 
Overview

Ethernet is available in different speeds (10/100/1000 and 10000Mbps) It provides ubiquitous connectivity to meet a wide range of needs from desktop PCs to switches. MorethanIP provides solutions for each Ethernet application with a library of configurable MAC (Media Access Control) and PCS (Physical Coding Sub-layer) Cores. The Tri-Mode Ethernet MAC core supports multiple applications including line cards, NIC cards and switching. It supports Full-Duplex Mode including transparent (for switching applications) and full Ethernet frame termination/generation (for NIC or line card applications).

Features
  • Full Featured Tri-Mode, 10/100 and Gigabit MAC with integrated FIFO
  • All Modes at all speeds UNH certified
  • Silicon Proven on eASIC Nextreme™ 90nm NEW ASIC

Ethernet 10/100

 
Overview

The Ethernet MAC (Media Access Control), is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standard. The MAC is handles the CSMA/CD protocol for transmission and reception of frames. It performs frame data encapsulation and de-capsulation, frame transmission and frame reception.

Features
  • The Ethernet IP Core consists of a number of individual modules including: The MAC (Media Access Control) module, formed by transmit,receive, and control modules
  • The MII (Media Independent Interface) Management module
  • The Host Interface
  • The Ethernet IP core uses three types of signals to connect to media:
  • WISHBONE signals to connect to the host interface
  • MII Management signals to connect to the PHY
  • Reset signals ( for resetting different parts of the Ethernet IP core)

Dual CAN 2.0B

 
Overview

The development of increasingly complex microsystems requires the usage of a powerful field bus systems for distributed real-time networks. The CAN protocol has a wide acceptance in the field of serial communication. The Dual CAN core is targeted to applications with two CAN core interfaces such as gateways. The Dual CAN bus controller core is described at the RTL system level which allows easy targeting of various technologies.

Features
  • Supports CAN Specification 2.0B (Standard and Extended Data and Remote Frames)
  • Two independent CAN cores with one hostcontroller interface
  • Programmable data rate up to 1 mbps
  • Programmable baud rate pre-scaler (up to 1/256)
  • Programmable internal 27-bit acceptance filtering for both CAN’s
  • 8-bit host-controller interface
  • Application specific interface to the hostcontroller on request (e.g. AMBA-APB)
  • Configurable interrupt sources
  • Special \”self test\” logic for test cases inserted
  • HDL design, complete synthesizable
  • Link to commercial bus drivers (for instance PCA82C250T by Philips)
  • Verified by the Bosch reference model

Common Platform Radio Interface (CPRI) Controller

 
Overview

The Common Public Radio Interface (CPRI) is an initiative to define a publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. CPRI allows the use of a distributed architecture where basestations, containing the REC, are connected to remote radio heads via lossless fibre links that carry the CPRI data. eASIC and Radiocomp now offers a complete easy-to-use intellectual property (IP) core for building CPRI v4.1 and lower interfaces to speed development time and allow you to focus on product differentiation. The IP core uses eASIC’s low power 6.5 Gbps MGIO transceivers to implement the CPRI Physical Layer and provides a compact and customizable Data Link Layer implemented in the eASIC logic fabric.

Features
  • Highly configurable
  • Built-in support for CPRI v4.1 REC and backwards compatible mapping methods
  • REC mode configuration support
  • Programmable line rates up to 6.144 Gbps as introduced in CPRI specification v4.1
  • Support for basic and advanced IQ data mapping modes
  • Up to 32 antenna carriers per IP core
  • 16-bit and lower sampling widths
  • Integrated 10/100 Ethernet MAC and HDLC controllers for control and management layers
  • WiMAX and WDCMA/LTE mapping support. Mapping
support for other standards is optional
  • Auxiliary port can be used to enable multi-hop system topologies
  • Source code license available for additional fee
  • Easy to use
  • Portable design to enable easy migration from FPGA to eASIC
  • Accurate delay measurement and calibration
  • Included test bench guides you through the operation of typical system configuration and provides example code for common CPRI start-up sequences

CAN 2.0B

 
Overview

The development of increasingly complex microsystems requires the usage of powerful field bus systems for distributed real-time networks. The CAN protocol has wide acceptance in the field of serial communication. The CAN bus controller core is described at the RTL system level which allows easy targeting of various technologies.

Features
  • Implementation of the Basic CAN specification
  • No generated Overload Frames
  • Receiving and transmitting of both identifiers (CAN specification 2.0B)
  • Programmable data rate up to 1 Mbps
  • Programmable baud rate pre-scaler (up to 1/30)
  • Application-specific interface to the host-controller
  • Link to commercial bus drivers (for instance, PCA82C250T by Philips)
  • Certified by Bosch reference model

AC97

 
Overview

This AC97 controller core provides an interface to an external AC97 audio codec thus enabling the implementation of CD quality audio Input/Output. The AC97 controller core supports one AC97 codec, with 6 output and 3 input channels.

Features
  • This AC97 controller core provides an interface to an external AC97 audio codec thus enabling the implementation of CD quality audio Input/Output
  • The AC97 controller core supports one AC97 codec, with 6 output and 3 input channels




Memory Controllers

UMMC DDR_X Controller

UMMC DDR_X Controller

 
Overview

The Mobiveil UMMC controller core supports various memory devices (DDR3, DDR4, LPDDR2 and LPDDR3). The core provides an interface module between memory devices and system side interfaces such as AXI, AHB, OCP or custom FIFO interfaces. It supports any mix of AXI, AHB, OCP or custom FIFO interfaces in an implementation. It allows the system to read from or write to the external memory without any knowledge of external memory type or protocol. The UMMC’s modular architecture is independent of system interfaces, PHY designs, implementation tools and most importantly the target technology.

Features
  • Supports multiple port sizes
  • For ports with AXI Interface
    • Compatibility with AMBA AXI protocol (AXI Version 1.0)
    • Support for AXI burst types: incremental and wrap
  • For ports with AHB interface
    • Compatibility with AMBA AHB specification, rev, 2.0
    • Support for all AHB burst types: single, incr, wrap
  • System interface clock asynchronous/synchronous to MC clock
  • System data bus width may be different from MC data bus width (Optional)
  • Supports QoS through various arbitration schemes
    • Round robin
    • Port priority and programmable bandwidth per port
    • Weighted round robin
  • Supports APB interface for Software/Configuration Register
  • Configurable and programmable address mapping
  • Configurable request queue depth
  • Configurable data buffer depth
  • Supports memory standards
    • DDR3
    • DDR4
    • LPDDR2
    • LPDDR3
  • Supports up to 4 ranks
  • Supports industry standard DFI 3.1 interface
    • Supports following MC clock to PHY clock ratio
      • 1:1 (Full-rate Mode)
      • 1:2 (Half-rate Mode)
      • 1:4 (Quarter rate Mode)
  • Supports different memory interface data width 8, 16, 32, 64 (72 with ECC enabled)
    • Supports 128-bit/256-bits memory interface data width (controllers operate in gang mode to access a 128-bit/256-bit memory device)
  • Supports different memory burst length 4, 8, 16
  • Supports partial population of memories where not all memory byte lanes are populated with memory chips
  • Supports active/precharge power down
  • Supports hardware/software driven self refresh entry and exit
  • Supports auto-refresh and per-bank refresh
  • Supports ECC checking and correction (optional)
    • With read modify write (partial write)
    • Without read modify write
  • Supports automated memory initialization
  • Supports ZQ calibration
  • Supports different request processing techniques
    • In-order request processing
    • Out of order request processing for better performance
  • Supports programmable memory timing parameters
  • Supports ODT
  • Supports intelligent request scheduling
    • Read/Write grouping
    • Refresh scheduling based on user traffic

eASIC DDR PHY

 
Overview

The combination of Northwest Logic’s Memory Controller Cores and ASIC DDR PHY is designed for use in eASICs Nextreme devices requiring high memory throughput, high clock rates and full pro-grammability. The core is fully silicon-proven in the eASIC Nextreme family of devices.

Features
  • Silicon-proven DDR PHY for use in eASIC NX devices
  • Supports DDR2, DDR, Mobile DDR SDRAM operation
  • Uses robust windowing data capture method
  • Uses internal eASIC DDR I/O and DLL
  • Supports ASIC-side ODT
  • Supports Byte and Nibble DQS
  • Supports a broad range of programmable features including timing, termination, drive strengths, etc.
  • Calibrated output and termination impedance
  • Comprehensive memory test support
  • Provided as a soft core with timing constraints enabling optimization for a target pinout
  • Customization and Integration services available

NAND FLASH Memory Controller

 
Overview

Implements a flexible controller for NAND flash memory devices from 2 to 128 Gb (single device). A smaller controller for up to 2 Gb devices is also available.

Features
  • Supports Single- and Multi-Level Cell (SLC and MLC) flash devices from 2 Gb to 32Gb for SLC and 128 Gb for MLC
  • The maximum memory space supported is 128 Gbits x 128 devices for a total of 2TB
  • Supports 2 kB and 4 kB page sizes for fast memory operations
  • Configurable number of banks has a maximum of 128
  • Command interface conforms to ONFI Standard 1.0 for compatibility with major manufacturers (e.g., Samsung, Micron, STMicroelectronics, etc.)
  • Configurable number of memory banks and devices per bank
  • Define number of chip select, ready/busy, and write protect signals.
  • Allows different memory for each bank
  • OCP 2.0 socket interface for easy integration with any system bus
  • Optional AMBA™ system interface wrapper supports AHB specification 2.0
  • 32-/16-/8-bits data transfers with 32-bit bus giving the advantage of higher throughput burst transfers support responses (OK, RETRY & SPLIT)Custom development of system bus wrappers
  • Adapts to a variety of system and memory types, with configurable timing parameters, 4/5 address cycles, 8/32 I/O memory support, ECC calculation turn on/off, Write/Erase Protection area and Interrupt enable/disable
  • Enables booting from flash, with configurable boot sequence

Mobile DDR SDRAM Core & Phy

 
Overview

Northwest Logic’s Mobile Mobile Double Data Rate (DDR) SDRAM Controller Cores is part of a complete Memory Interface Solution including Add-On Cores and eASIC specific DDR PHY. This solution provides very high Mobile DDR SDRAM bus performance with minimal latency. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core fully supports the eASIC Nextreme and NExtreme-2 families of devices. Northwest Logic’s Mobile DDR SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Features
  • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
  • Minimal latency achieved via parameterized pipelining
  • Achieves high clock rates with minimal routing constraints
  • Supports full rate and half-rate clock operation
  • Full run-time configurable timing parameters and memory settings
  • Supports self-refresh, partial array self-refresh, power-down and deep power down modes
  • Supports 2T timing
  • Full set of Add-On Cores available
  • Delivered fully integrated and verified with target DDR PHY
  • Minimal ASIC gate count
  • Source code available
  • Customization and Integration services available

SPI Master

 
Overview

Synchronous serial interfaces are widely used to provide board-level interfaces between different devices such as microcontrollers, DACs and ADCs and. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations, namely, SPI and Microwire/Plus.

Features
  • Full duplex synchronous serial data transfer
  • Variable length of transfer word up to 128 bits
  • MSB or LSB first data transfer
  • Technology independent Verilog
  • Fully synthesizable
  • Rx and Tx on both rising or falling edge of serial clock independently
  • 8 slave select lines
  • Fully static synchronous design with one clock domain
  • Technology independent Verilog

DDR3 SDRAM Controller Core & Phy

 
Overview

Northwest Logic’s Double Data Rate 2 (DDR2) SDRAM Controller Core is part of a complete Memory Interface Solution including Add-On Cores and eASIC specific DDR PHY. This solution provides very high DDR2 SDRAM bus performance with minimal latency. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core is fully silicon-proven in the eASIC Nextreme and Nextreme-2 families of devices. Northwest Logic’s DDR2 SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Features
  • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
  • Minimal latency achieved via parameterized pipelining
  • Achieves high clock rates with minimal routing constraints
  • Supports full rate and half-rate clock operation
  • Full run-time configurable timing parameters and memory settings
  • Supports ODT and 2T timing
  • Full set of Add-On Cores available
  • Delivered fully integrated and verified with target DDR PHY
  • Minimal ASIC gate count
  • Source code available
  • Customization and Integration services available

DDR2 SDRAM Controller Core & Phy

 
Overview

Northwest Logic’s Double Data Rate 2 (DDR2) SDRAM Controller Core is part of a complete Memory Interface Solution including Add-On Cores and eASIC specific DDR PHY. This solution provides very high DDR2 SDRAM bus performance with minimal latency. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core is fully silicon-proven in the eASIC Nextreme and Nextreme-2 families of devices. Northwest Logic’s DDR2 SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Features
  • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
  • Minimal latency achieved via parameterized pipelining
  • Achieves high clock rates with minimal routing constraints
  • Supports full rate and half-rate clock operation
  • Full run-time configurable timing parameters and memory settings
  • Supports ODT and 2T timing
  • Full set of Add-On Cores available
  • Delivered fully integrated and verified with target DDR PHY
  • Minimal ASIC gate count
  • Source code available
  • Customization and Integration services available

DDR SDRAM Controller Core & Phy

 
Overview

The Northwest Logic DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core fully supports the eASIC Nextreme-2 family of devices.

Features
  • Provides high performance, scatter-gather DMA operation
  • Works with Northwest Logic Expresso Cores and FPGA PCI Express hard cores
  • Can be configured with multiple independent DMA Engines
  • Supports Packet/Block and Addressed/Non-addressed transfers
  • Provides simple Target and Register interfaces
  • Supports 32 and 64 bit system addressing
  • Supports legacy, MSI, MSI-X interrupts
  • Fully hardware validated and PCI-SIG certified
  • Companion Windows and Linux DMA Drivers available
  • Provided with a PCI Express Testbench
  • Delivered fully integrated with target PCI Express core
  • Minimal ASIC gate count
  • Source code available
  • Customization and Integration services available
DDR2 Controller

DDR2 Controller

 
Overview

ASIC Architect's DDR and DDR2 Controller IP Cores are an integral part of the product portfolio aimed at providing a complete end-to-end solution in the High Speed Interface Controller domain. The DDR and DDR2 Controller Cores are architected, designed and verified by ASIC/SoC industry veterans. The add-on solution cores that come with the DDR Controller, accelerate the chip-level integration by connecting multiple clients to the DDR Controller.

Features
  • Supports up to 533MHz in DDR2 Mode
  • Powerful Application Interface
  • Supports both DDR and DDR2 JEDEC Standards
  • Addressing capability upto 4GB DDR2 devices
  • Programmable Features:
    • Memory timing parameters – Tras, Trdl, Tccd, Trfc, Tmrd, Trp, Tcrd
    • Intelligent Bank Management
    • Supports buffered and unbuffered DIMMs
    • Supports On-die termination (ODT), and Off-Chip Driver impedance adjustment
  • Configurable Features:
    • Address Mapping between application bus and row/column/bank addresses
    • Choice of 16/32/64-bit DDR bus-width
    • Size of Command Queue
  • Supports additive CAS latency feature to maximize command bus utilization
  • Supports Back-to-Back WR & RD with minimum time intervals
  • High data rate up to 100% memory throughput
  • Byte-wide optional ECC Support
  • Auto initialization of DDR Memories
  • Byte-Wide Data Mask Support
  • Self-refresh and power down control
  • Fully ATPG Testable – Multiple Clock Domains
  • Supports industry standard memory vendors
  • Low Latency
  • Verified with leading memory and IO vendors
  • Supports Multiple Application Clients
  • Optionally connects to AMBA® 3 AXI™ bus




Microprocessors & Peripherals

eSi-1600

 
Overview

EnSilica’s eSi-1600 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into eASIC Nextreme-2 devices. It offers similar performance to more expensive 32-bit CPUs, while having a system cost comparable to that of 8-bit CPUs. Significant power savings are possible compared to 8-bit CPUs as applications require far fewer clock cycles to run.

Features
  • 16-bit RISC architecture
  • 16 general purpose registers
  • 92 basic instructions and 10 addressing modes
  • Supports up to 90 user-defined instructions
  • 5-stage pipeline
  • Harvard or von Neumann memory architecture
  • AMBA AHB and APB peripheral bus
  • Optional support for user and supervisor modes
  • Up to 16 interrupts plus NMI and system call
  • Fast interrupt response time of 6-9 cycles
  • JTAG or serial debug
  • High code density
  • C and C++ software development using license-free toolchain, under industry standard Eclipse IDE
  • Easy migration path to 32-bit version

eSi-3200

 
Overview

EnSilica’s eSi-3200 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into eASIC Nextreme-2 devices. The eSi-3200 is particularly suited to embedded control applications.

Features
  • 32-bit RISC architecture
  • 16 or 32 general purpose registers
  • 104 basic instructions and 10 addressing modes
  • Supports up to 90 user-defined instructions
  • 5-stage pipeline
  • Harvard or von Neumann memory architecture
  • Optional memory protection unit (MPU)
  • AMBA AXI or AHB data bus and APB peripheral bus
  • Optional support for user and supervisor modes
  • Up to 32 interrupts plus NMI and system call
  • Fast interrupt response time of 6-9 cycles
  • JTAG or serial debug
  • Intermixed 16 and 32-bit instructions result in exceptional code density without compromising performance
  • C and C++ software development using license-free toolchain, under industry standard Eclipse IDE
  • Easy migration path to 16-bit version or 32-bit version with caches

LEON4 Processor

 
Overview

The LEON4 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-chip (SOC) designs. LEON4 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The LEON4 is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Aeroflex Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and eASIC device technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL, MAC and DIV instructions and an optional IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU). The LEON4 cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications. The LEON4 pipeline uses 64-bit internal load/store data paths, with an AMBA AHB interface of either 64- or 128-bit. Branch prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1.7 DMIPS/MHz, or 2.1 CoreMark/MHz.

Features
  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline, with branch prediction
  • 64-bit single-clock load/store operation
  • 64-bit 4-port register file
  • Hardware multiply, divide and MAC units
  • High-performance, fully pipelined IEEE-754 FPU
  • Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Configurable caches L1: 1 – 4 ways, 1 – 256 kbytes/way. Random, LRR or LRU replacement
  • Configurable L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte – 8 Mbyte
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA-2.0 AHB bus interface, 64- or 128-bit wide
  • Advanced on-chip debug support with instruction and data trace buffer, and performance counter
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Up to 150 MHz in FPGA and 1500 MHz on 32 nm eASIC device technologies
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • High performance: 1.7 DMIPS/MHz, 2.1 CoreMark/MHz, 0.35 SPECint2000/MHz

ColdFire V2 Processor

 
Overview

The V2 ColdFire Core is one of the smallest 32-bit processors available today while still providing industry leading performance. Freescale MCF52xx devices built from the V2 ColdFire Core can be found in health care instrumentation, point-of-sale terminals, factory automation, fire and security systems, and many other industrial and consumer applications.

Features
  • Variable-length RISC, clock-multiplied core
  • 166-MHz in typical 130-nm process
  • Independent, decoupled pipelines:
  • 2-stage instruction fetch pipeline (IFP)
  • 2-stage operand execution pipeline (OEP)
  • FIFO instruction buffer is the decoupling mechanism
  • 16 user-accessible, 32-bit general purpose registers (GPRs)
  • 32-bit data bus & 32-bit address bus supporting 4-GB linear addressing range
  • Sophisticated two-level branch acceleration mechanisms minimize change-of-flow execution time
  • Background Debug Mode (BDM), Real-Time Trace (RTT), and Real-Time Debug (RTD) support
  • Binary object code compatibility across the entire Freescale ColdFire Family
  • Optional Enhanced Multiply-Accumulate (EMAC) provides high-speed signal processing capabilities with four 40-bit accumulators and single-cycle instruction issue rate on 32-bit MAC operations
  • Vector base register to relocate the exception vector table
  • Integrated cache controller; cache is direct-mapped, configurable as instruction, data, or split instruction/data cache
  • Integrated SRAM controller
  • 100% synthesizable and technology-independent design
  • EDA tool-neutral packaging

ColdFire V1 Processor

 
Overview

The V1 ColdFire instruction set includes special MAC/DIV instructions executed in dedicated MAC/DIV hardware. It also provides improved handling of byte (8-bit) and word (16-bit) operands and offers upward compatibility with other ColdFire cores such as the V2.

Features
  • 32-bit processor core with 24-bit address bus
  • Unified instruction/data bus (AMBA 2 AHB)
  • Single-wire debug interface
  • Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
  • Independent, decoupled pipelines
  • 2-stage Instruction Fetch Pipeline (IFP)
  • 2-stage Operand Execution Pipeline (OEP)
  • FIFO Instruction Buffer is the decoupling mechanism
  • ColdFire Instruction Set Architecture Rev. C (ISA_C)
  • Standard ColdFire user programming model with 16 general-purpose, 32-bit registers
  • Simplified supervisor programming model supporting a supervisor stack pointer, vector base register, and CPU configuration register
  • Static branch prediction mechanisms minimize change-of-flow execution time
  • Execute engines include ALU, barrel shifter, integer divider (DIV), and multiply accumulate unit (MAC)
  • Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)

1200 Processor

 
Overview

OpenRISC 1200 Processor is part of the OR1000 architecture of free, open source RISC processor cores. The OR1200 processor is a 32-bit load and store RISC architecture designed with emphasis on performance,simplicity, low power, scalability and versatility.

Features
  • Free 32-bit processor
  • Harvard architecture
  • Very silicon efficient
  • Multiple instantiation possible on eASIC Nextreme Structured ASIC
  • Supported by open source software GNU tools
  • Id GNU Compiler
  • As GNU Assembler
  • GDB GNU Debugger

LEON3 Processor

 
Overview

LEON3 is a 32-bit processor core conforming to the IEEE-1754 (SPARC V8) architecture. It is designed for embedded applications, combining high performance with low complexity and low power consumption.

Features
  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline
  • Hardware multiply, divide and MAC units
  • High-performance, fully pipelined IEEE-754 FPU
  • Separate instruction and data cache (Harvard architecture) with snooping
  • Configurable caches: 1 – 4 sets, 1 – 256 kbytes/set. Random, LRR or LRU replacement
  • Local instruction and data scratch pad rams
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA-2.0 AHB bus interface
  • Advanced on-chip debug support with instruction and data trace buffer
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • 235MHz typical performance in eASIC Nextreme zero mask-charge ASIC
  • Fault-tolerant and SEU-proof version available for space applications
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors

AMBA IP Library

 
Overview

The PIP-AMBA provides the essential IP cores and infrastructure software needed for AMBA bus systems. Ready for software development out of the box but also easy to customize and extend, it serves as a basic platform for the rapid development of a variety of system-on-chip (SOC) applications. The platform is well suited to a variety of AMBA based SoC designs. It includes the multi-master and arbitration features of the high-performance AHB bus, and a bridge to the slower APB peripherals bus. The architecture makes it straightforward to add additional IP cores or custom logic to either bus.

Features
  • Integrated IP cores and software subsystem provides basic infra-structure for many SoC applications
  • Platform saves significant time over acquiring and integrating separate elements
  • Works with low-power, 32-bit Tensilica processors
  • Built on AMBA standard bus for broad applicability
  • Enables both the high-performance AHB and the APB peripherals buses
  • Easily add custom logic or additional IP cores to tailor or expand the system
  • Immediately begin software development and test
  • Supports Tensilica® RealView®, GNU and other development tools
  • Complete infrastructure includes essential hardware and software
  • Included IP cores:
    • Microprocessor interface
    • APB Bridge
    • Timers
    • Scalable Interrupt Controller
    • Parallel I/O
    • Internal SRAM with Controller
  • Software
    • boot code
    • Interrupt Service (ISR) code
    • Main code with Scheduler
    • Device driver code
    • Hardware Level API
  • Plug-in architecture for user-defined custom IP blocks
  • Support for real-time operating systems (RTOS)
    • AMBA Bus Functional Model with support for interrupts and subroutines
    • Sophisticated HDL Testbench with external models and interfaces
    • System Level Simulation scripts, C-test/Macro test code and comparison utilities
  • Complete user documentation




Video & Image Processing

4:2:2 to 4:2:0 Converter

 
Overview

This Core Values™ parametrizable product converts 4:2:2 video with external syncs to 4:2:0 video with external syncs using an external memory.

Features
  • Accepts 4:2:2 video of any resolution
  • Outputs 4:2:0 video at the input resolution
  • Interfaces directly to external syncs
  • Accepts Progressive or Interlaced Video
  • Parametrizable input/output bit width
  • Customized memory interface to video resolution
  • Sample output images and video available
  • Linted and Verified Verilog 2001 Source Code
  • Permanent Company License (not per-project)

YCbCr to RGB SD Color Space Converter

 
Overview

This Core Values™ product converts 4:2:2 YCbCr video to 4:4:4 RGB video.

Features
  • Converts 10-bit Standard Definition 4:2:2 YCbCr Video
  • Outputs 4:4:4 13.5 MHz 10-bit 0-255 RGB Video
  • Internal 23-bit precision
  • CbYCrY 27 MHz 16-240/235 10-bit video input
  • CCIR 601 Color Space Converter
  • Linted and Verified Verilog 2001 Source Code
  • Permanent Company License (not per-project)

YCbCr to RGB HD Color Space Converter

 
Overview

This Core Values™ product converts 4:2:2 YCbCr HD video to 4:4:4 RGB video.

Features
  • Converts High Definition 4:2:2 YCbCr Video
  • Outputs 4:4:4 RGB Video
  • Parameterizable Internal M-bit precision
  • Parametrizable I/O N-bit precision
  • Follows ITU-R Recommendation BT.709
  • Linted and Verified Verilog 2001 Source Code
  • Permanent Company License (not per-project)

SMPTE 274M/296M Encoder

 
Overview

This Core Values™ encoder allows designs with internal 1080i or 720p 4:2:2 YCbCr High Definition 20-bit video and data buses to connect to devices that receive SMPTE 274M/296M 74.25 MHz and 74.25/1.001 MHz 20-bit data with embedded syncs.

Features
  • Encodes to SMPTE 274M/296M, HD 1080i/720p
  • Supports 50 Hz, 59.94 Hz and 60 Hz
  • Acts as master to video-and-data-plus-sync logic
  • Signals VANC ancillary data period for data insertion
  • Signals HANC ancillary data period with HBLANKING
  • Clamps active video to valid non-sync values
  • Linted Verilog 2001 Source Code
  • Permanent Company License (not per-project)

SMPTE 274M/296M Decoder

 
Overview

This Core Values™ encoder allows designs to receive SMPTE 274M/296M 74.25 MHzand 74.25/1.001 MHz 20-bit data with embedded syncs.

Features
  • Decodes HD SMPTE 274M (1080i/p), 296M (720p)
  • Detects 24, 50 Hz and 59.94/60 Hz timings
  • Produces video-and-data-plus-sync to external logic
  • Extracts H, V, F , HANC and VANC ancillary data
  • Detects 22 different errors in embedded stream
  • Detects 1080i/p and 720p with Lock signal
  • Linted Verilog 2001 Source Code
  • Permanent Company License (not per-project)

ITU-R 656-4 Encoder

 
Overview

This Core Values™ encoder allows designs with internal 4:2:2 YCbCr Standard Definition 20-bit video and 10-bit ancillary data buses connect to devices that receive ITU-R 656 27MHz NTSC and PAL 10-bit data with embedded syncs.

Features
  • Encodes to ITU-R 656-4
  • Supports 50Hz/625 and 60/525 video
  • Acts as master to video-and-data-plus-sync logic
  • Signals HANC and VANC ancillary data periods for data insertion
  • Clamps active video to valid non-sync values
  • Linted Verilog 2001 Source Code
  • Permanent Company License (not per-project)

ITU 656-4 Decoder

 
Overview

This decoder allows designs to connect to devices that send 10-bit wide 27 MHz Standard Definition media streams with embedded syncs and auto-detects 525-line or 625-line video.

Features
  • Decodes ITU-R 656-4 parallel streams
  • Extracts Luma, Chroma and Ancillary Data
  • Extracts F, V and H synchronization signals
  • Checks for possible errors in parallel stream
  • Signals 625 line detection
  • HANC/VANC, Valid Ancillary Data signaling
  • Linted and Verified Verilog 2001
  • Permanent Company License (not per-project)
  • ASIC or FPGA Applications

2D Down Scaler

 
Overview

This Core Values™ product horizontally down-scales interlaced or progressive images. The core is customized for your specific application and no logic is wasted on resolutions that are not needed. For example you can start with an SD NTSC input (720x487i) and horizontally down-scale to a VGA sized output (640x487i) for more efficient MPEG/H.264 encoding or to adapt to a certain display Horizontal resolution. Implementations are available with single-macroblock resolution and precision is parametrizable for quality/size decisions.

Features
  • Down-scales directly RGB images of any bit depth
  • Interfaces to 4:4:4/4:2:2 YCbCr data with converters
  • Customized to any desired input/output size
  • Converts between square and rectangular pixels
  • Parametrizable Input, Processing, Output precision
  • Macroblock boundaries: 720:704, 720:640, etc.
  • Sample output images available for evaluation
  • Linted and Verified Verilog 2001 Source Code
  • Permanent Company License (not per-project)

RGB Horizontal Down Scaler

 
Overview

This Core Values™ product horizontally down-scales interlaced or progressive images. The core is customized for your specific application and no logic is wasted on resolutions that are not needed. For example you can start with an SD NTSC input (720x487i) and horizontally down-scale to a VGA sized output (640x487i) for more efficient MPEG/H.264 encoding or to adapt to a certain display Horizontal resolution. Implementations are available with single-macroblock resolution and precision is parametrizable for quality/size decisions.

Features
  • Down-scales directly RGB images of any bit depth
  • Interfaces to 4:4:4/4:2:2 YCbCr data with converters
  • Customized to any desired input/output size
  • Converts between square and rectangular pixels
  • Parametrizable Input, Processing, Output precision
  • Macroblock boundaries: 720:704, 720:640, etc.
  • Sample output images available for evaluation
  • Linted and Verified Verilog 2001 Source Code
  • Permanent Company License (not per-project)

VGA Controller Core

 
Overview

The OpenCores VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost all available LCD and CRT displays.

Features
  • CRT and LCD display support
  • 24-bit Standard VGA interface
  • Separate VSYNC/HSYNC and combined CSYNC synchronization signals
  • Composite BLANK signal
  • TripleDisplay support
  • 12-bit Interface compatible with DVI transmitters and 12-bit VGA ADCs
  • User programmable video resolutions, video timing and video control signals
polarization levels
  • 32bpp, 24bpp and 16bpp color modes
  • 8bit gray-scale and 8bit pseudo-color modes
  • Supports video- and/or color-lookup-table bank switching during vertical retrace

VGA/SVGA Display Controller Core

 
Overview

The VGA accepts video data and works with a digital/analog converter (DAC) to drive standard VGA and SVGA displays. The core’s system interface uses the AMBA AHB bus. It accepts two different standard input formats – 15-bit (5:5:5) and 24-bit (8:8:8) RGB – and produces 24-bit RGB pixel data.

Features
  • Generates color and control data for standard VGA/SVGA displays
  • Works in conjunction with external video DAC such as Analog Devices’ ADV7120
  • Supports resolution up to 1024 x 1024 (higher resolutions available upon request)
  • Accepts two standard video data formats:
  • 24-bit RBG (8:8:8)
  • 15-bit RBG (5:5:5)
  • Outputs standard 8:8:8 24-bit RGB video (converts from 5:5:5 if necessary)
  • Display functions with hardware support:
  • Scroll (in horizontal and vertical directions)
  • Sub-screen display (any position)
  • Horizontal flip screen
  • Fully configurable monitor frequencies and aspect ratios
  • 32-bit data path
  • Configurable internal FIFO
  • Integrated Test mode: core generates color bar without any AHB bus transactions
  • Internal, event-stimulated, interrupt request generation with masking capability
  • Dedicated unidirectional DMA controller with burst transaction support
  • Built-in Power Save mode
  • Requires an external pixel clock.
  • Integrated with AMBA™ bus:
  • AMBA™ AHB slave unit interfaces with host controller
  • AMBA™ AHB master unit interfaces with host memory

H.264 Encoder

 
Overview

The H.264 core is compliant with the H.264 Advanced Video Coding (AVC) Baseline profile video compression algorithm (level 4.1). It can process up to 32 frame-multiplexed video channels, and each channel may have its own resolution and frame rate. With its ability to process multiple inputs and unusual support for frame sizes up through HDTV at fast transmission rates, the H.264-E core is especially effective for multi-camera surveillance systems, video conferencing packages, networked camera situations, and any application with multiple video sources feeding into a single network node where bandwidth is limited.

Features
  • Meets the ITU-T H.264 baseline specification
  • Profile level 4.1 (output can be read by a Main Profile decoder)
  • Supports common video resolutions with very low operational frequencies, e.g:
  • 720p HDTV progressive (1280×720) @ 30fps requires about 110 MHz
  • Supports up to 32 frame-multiplexed video channels; each may have a different resolution and frame rate
  • Independent hardware encoder processes video without assistance of a microprocessor
  • Supports YCbCr 4:2:0 16×16 block video input
  • Supports most intra4x4 and all intra16x16 modes
  • Flexible output:
  • Constant Bit Rate (CBR) for applications with limited bandwidth
  • Variable Bit Rate (VBR) for low latency and detailed images in fast-changing scenes
  • Motion vector up to -16.00/+15.75 pixels (search area is 32×32 pixel wide down to quarter pixel)
  • Supports multiple slices for better error resilience
  • Block skipping logic for lower bit rate
  • Very low latency in VBR mode (~1 ms for VGA @ 30 fps)
  • Deblocking filter for better quality, especially at low bit rates